Updated April 2019
J. T. Teherani, “(Invited) Orientation Dependence of the Hole Ballistic Velocity in Si, SiGe, and Ge Thin-Body Structures with Uniaxial Compressive Strain,” ECS Fall Meeting, Cancun, Mexico, 2018, vol. MA2018-02, pp. 1017–1017. http://ma.ecsdl.org/content/MA2018-02/31/1017
J. T. Teherani, “The Auger FET: a Novel Device Concept for Subthermal Switching,” IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM), 2018, pp. 208–210. https://doi.org/10.1109/EDTM.2018.8421442
A. Nipane, Y. Zhang, and J. T. Teherani, “Role of out-of-plane dielectric thickness in the electrostatic simulation of atomically thin lateral junctions,” Journal of Applied Physics, vol. 123, no. 21, p. 214302, Jun. 2018. https://doi.org/10.1063/1.5027520
A. Nipane, S. Jayanti, A. Borah, and J. T. Teherani, “Erratum: ‘Electrostatics of lateral p-n junctions in atomically thin materials,’” Journal of Applied Physics, vol. 124, no. 13, p. 139902, Oct. 2018. https://doi.org/10.1063/1.5051548
Y. Jung, M. S. Choi, A. Borah, A. Nipane, W. J. Yoo, J. Hone, and J. T. Teherani, “Reliable High-Quality Metal-Embedded h-BN Contacts to p-type WSe2,” 76th Device Research Conference (DRC), 2018, pp. 1–2. https://doi.org/10.1109/DRC.2018.8442181
M. S. Choi, Y. Jung, D. Rhodes, B. Kim, J. T. Teherani, J. Hone, and W. J. Yoo, “Study of Contact Properties for Semiconducting TMDCs Using Via Contacts Embedded in h-BN,” Bulletin of the American Physical Society, Los Angeles, California, 2018. http://meetings.aps.org/Meeting/MAR18/Session/T60.169
A. Borah, P. J. Sebastian, A. Nipane, and J. T. Teherani, “An Intuitive Equivalent Circuit Model for Multilayer Van Der Waals Heterostructures,” IEEE Transactions on Electron Devices, vol. 65, no. 10, pp. 4209–4215, Oct. 2018. https://doi.org/10.1109/TED.2018.2851920
J. T. Teherani, “A Comprehensive Theoretical Analysis of Hole Ballistic Velocity in Si, SiGe, and Ge: Effect of Uniaxial Strain, Crystallographic Orientation, Body Thickness, and Gate Architecture,” IEEE Transactions on Electron Devices, vol. 64, no. 8, pp. 3316–3323, Aug. 2017. https://doi.org/10.1109/TED.2017.2708691
A. Nipane, S. Jayanti, A. Borah, and J. T. Teherani, “Electrostatics of lateral p-n junctions in atomically thin materials,” Journal of Applied Physics, vol. 122, no. 19, p. 194501, Nov. 2017. https://doi.org/10.1063/1.4994047
A. Kerelsky, A. Nipane, D. Edelberg, D. Wang, X. Zhou, A. Motmaendadgar, H. Gao, S. Xie, K. Kang, J. Park, J. T. Teherani, and A. Pasupathy, “Absence of a Band Gap at the Interface of a Metal and Highly Doped Monolayer MoS2,” Nano Lett., Sep. 2017. https://doi.org/10.1021/acs.nanolett.7b01986
A. Kerelsky, A. Nipane, D. Edelberg, D. Wang, M. Cheng, A. Dadgar, H. Gao, K. Kang, J. Park, J. T. Teherani, and A. Pasupathy, “Band Structure Evolution in Vertically Contacted MoS2 Probed Using Scanning Tunneling Spectroscopy,” Bulletin of the American Physical Society, New Orleans, Louisiana, 2017, vol. Volume 62, Number 4. http://meetings.aps.org/Meeting/MAR17/Session/L32.12
J. T. Teherani, S. Agarwal, W. Chern, P. M. Solomon, E. Yablonovitch, and D. A. Antoniadis, “Auger generation as an intrinsic limit to tunneling field-effect transistor performance,” Journal of Applied Physics, vol. 120, no. 8, p. 084507, Aug. 2016. https://doi.org/10.1063/1.4960571
J. T. Teherani, “Fundamental limits of the switching abruptness of tunneling transistors,” Thesis, Massachusetts Institute of Technology, 2015. https://doi.org/1721.1/99853
J. T. Teherani, W. Chern, S. Agarwal, J. L. Hoyt, and D. A. Antoniadis, “A framework for generation and recombination in tunneling field-effect transistors,” Fourth Berkeley Symposium on Energy Efficient Electronic Systems (E3S), 2015, pp. 1–3. https://doi.org/10.1109/E3S.2015.7336797
T. Yu, J. T. Teherani, D. A. Antoniadis, and J. L. Hoyt, “Effects of substrate leakage and drain-side thermal barriers in In0.53Ga0.47As/GaAs0.5Sb0.5 quantum-well tunneling field-effect transistors,” Appl. Phys. Express, vol. 7, no. 9, p. 094201, Sep. 2014. https://doi.org/10.7567/APEX.7.094201
J. T. Teherani, W. Chern, D. A. Antoniadis, and J. L. Hoyt, “Ultra-Thin, High Quality HfO2 on Strained-Ge MOS Capacitors with Low Leakage Current,” ECS Trans., vol. 64, no. 6, pp. 267–271, Aug. 2014. https://doi.org/10.1149/06406.0267ecst
W. Chern, P. Hashemi, J. T. Teherani, D. A. Antoniadis, and J. L. Hoyt, “Record Hole Mobility at High Vertical Fields in Planar Strained Germanium on Insulator With Asymmetric Strain,” IEEE Electron Device Letters, vol. 35, no. 3, pp. 309–311, Mar. 2014. https://doi.org/10.1109/LED.2014.2300197
S. Agarwal, J. T. Teherani, J. L. Hoyt, D. A. Antoniadis, and E. Yablonovitch, “Engineering the Electron-Hole Bilayer Tunneling Field-Effect Transistor,” IEEE Transactions on Electron Devices, vol. 61, no. 5, pp. 1599–1606, May 2014. https://doi.org/10.1109/TED.2014.2312939
T. Yu, J. T. Teherani, D. A. Antoniadis, and J. L. Hoyt, “InGaAs/GaAsSb Quantum-Well Tunnel-FETs With Tunable Backward Diode Characteristics,” IEEE Electron Device Letters, vol. 34, no. 12, pp. 1503–1505, 2013. https://doi.org/10.1109/LED.2013.2287237
J. T. Teherani, T. Yu, D. A. Antoniadis, and J. L. Hoyt, “Electrostatic design of vertical tunneling field-effect transistors,” Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S), 2013, pp. 1–2. https://doi.org/10.1109/E3S.2013.6705872
J. T. Teherani and J. L. Hoyt, “A Physically-Intuitive Method for Calculation of the Local Lattice Constant from a High-Resolution Transmission Electron Microscopy Image by Fourier Analysis,” arXiv, Sep. 2013. http://arxiv.org/abs/1309.3155
J. T. Teherani, W. Chern, D. A. Antoniadis, and J. L. Hoyt, “Simulation of enhanced hole ballistic velocity in asymmetrically strained Germanium nanowire trigate p-MOSFETs,” IEEE International Electron Devices Meeting (IEDM), 2013, pp. 32.4.1-32.4.4. https://doi.org/10.1109/IEDM.2013.6724737
J. T. Teherani, S. Agarwal, E. Yablonovitch, J. L. Hoyt, and D. A. Antoniadis, “Impact of Quantization Energy and Gate Leakage in Bilayer Tunneling Transistors,” IEEE Electron Device Letters, vol. 34, no. 2, pp. 298–300, Feb. 2013. https://doi.org/10.1109/LED.2012.2229458
S. Agarwal, J. T. Teherani, J. L. Hoyt, D. A. Antoniadis, and E. Yablonovitch, “Optimization of the electron hole bilayer tunneling field effect transistor,” 71st Device Research Conference (DRC), 2013, pp. 109–110. https://doi.org/10.1109/DRC.2013.6633817
J. T. Teherani, W. Chern, D. A. Antoniadis, J. L. Hoyt, L. Ruiz, C. D. Poweleit, and J. Menéndez, “Extraction of large valence-band energy offsets and comparison to theoretical values for strained-Si/strained-Ge type-II heterostructures on relaxed SiGe substrates,” Phys. Rev. B, vol. 85, no. 20, p. 205308, May 2012. https://doi.org/10.1103/PhysRevB.85.205308
P. Hashemi, W. Chern, H. Lee, J. T. Teherani, Y. Zhu, J. Gonsalvez, G. G. Shahidi, and J. L. Hoyt, “Ultrathin Strained-Ge Channel P-MOSFETs With High-K/Metal Gate and Sub-1-nm Equivalent Oxide Thickness,” IEEE Electron Device Letters, vol. 33, no. 7, pp. 943–945, Jul. 2012. https://doi.org/10.1109/LED.2012.2195631
W. Chern, P. Hashemi, J. T. Teherani, T. Yu, Y. Dong, G. Xia, D. A. Antoniadis, and J. L. Hoyt, “High mobility high-K-all-around asymmetrically-strained Germanium nanowire trigate p-MOSFETs,” IEEE International Electron Devices Meeting (IEDM), 2012, pp. 16.5.1-16.5.4. https://doi.org/10.1109/IEDM.2012.6479055
P. M. Solomon, I. Lauer, A. Majumdar, J. T. Teherani, M. Luisier, J. Cai, and S. J. Koester, “Effect of Uniaxial Strain on the Drain Current of a Heterojunction Tunneling Field-Effect Transistor,” Electron Device Letters, IEEE, vol. 32, no. 4, pp. 464–466, 2011. https://doi.org/10.1109/LED.2011.2108993
J. T. Teherani, “Band-to-band tunneling in silicon diodes and tunnel transistors,” Thesis, MIT, Cambridge, MA, USA, 2010. https://doi.org/1721.1/60215
P. Hashemi, J. T. Teherani, and J. L. Hoyt, “Investigation of hole mobility in gate-all-around Si nanowire p-MOSFETs with high-K/metal-gate: Effects of hydrogen thermal annealing and nanowire shape,” IEEE International Electron Devices Meeting (IEDM), 2010, pp. 34.5.1-34.5.4. https://doi.org/10.1109/IEDM.2010.5703477
J. Beck, R. Scritchfield, B. Sullivan, J. T. Teherani, C.-F. Wan, M. Kinch, M. Ohlson, M. Skokan, L. Wood, P. Mitra, M. Goodwin, and J. Robinson, “Performance and modeling of the MWIR HgCdTe electron avalanche photodiode,” Proceedings of the SPIE, 2009, vol. 7298, pp. 729838-729838–17. https://doi.org/10.1117/12.819045
J. Beck, R. Scritchfield, B. Sullivan, J. T. Teherani, C.-F. Wan, M. Kinch, M. Ohlson, M. Skokan, L. Wood, P. Mitra, M. Goodwin, and J. Robinson, “Performance and Modeling of the MWIR HgCdTe Electron Avalanche Photodiode,” Journal of Elec Materi, vol. 38, no. 8, pp. 1579–1592, Aug. 2009. https://doi.org/10.1007/s11664-009-0684-8
H. F. Schaake, M. A. Kinch, D. Chandra, F. Aqariden, P. K. Liao, D. F. Weirauch, C.-F. Wan, R. E. Scritchfield, W. W. Sullivan, J. T. Teherani, and H. D. Shih, “High-Operating-Temperature MWIR Detector Diodes,” Journal of Elec Materi, vol. 37, no. 9, pp. 1401–1405, Sep. 2008. https://doi.org/10.1007/s11664-008-0423-6
J. T. Teherani, “The Auger FET: a Novel Device Concept for Subthermal Switching,” IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM), 2018, pp. 208–210. https://doi.org/10.1109/EDTM.2018.8421442
A. Nipane, Y. Zhang, and J. T. Teherani, “Role of out-of-plane dielectric thickness in the electrostatic simulation of atomically thin lateral junctions,” Journal of Applied Physics, vol. 123, no. 21, p. 214302, Jun. 2018. https://doi.org/10.1063/1.5027520
A. Nipane, S. Jayanti, A. Borah, and J. T. Teherani, “Erratum: ‘Electrostatics of lateral p-n junctions in atomically thin materials,’” Journal of Applied Physics, vol. 124, no. 13, p. 139902, Oct. 2018. https://doi.org/10.1063/1.5051548
Y. Jung, M. S. Choi, A. Borah, A. Nipane, W. J. Yoo, J. Hone, and J. T. Teherani, “Reliable High-Quality Metal-Embedded h-BN Contacts to p-type WSe2,” 76th Device Research Conference (DRC), 2018, pp. 1–2. https://doi.org/10.1109/DRC.2018.8442181
M. S. Choi, Y. Jung, D. Rhodes, B. Kim, J. T. Teherani, J. Hone, and W. J. Yoo, “Study of Contact Properties for Semiconducting TMDCs Using Via Contacts Embedded in h-BN,” Bulletin of the American Physical Society, Los Angeles, California, 2018. http://meetings.aps.org/Meeting/MAR18/Session/T60.169
A. Borah, P. J. Sebastian, A. Nipane, and J. T. Teherani, “An Intuitive Equivalent Circuit Model for Multilayer Van Der Waals Heterostructures,” IEEE Transactions on Electron Devices, vol. 65, no. 10, pp. 4209–4215, Oct. 2018. https://doi.org/10.1109/TED.2018.2851920
J. T. Teherani, “A Comprehensive Theoretical Analysis of Hole Ballistic Velocity in Si, SiGe, and Ge: Effect of Uniaxial Strain, Crystallographic Orientation, Body Thickness, and Gate Architecture,” IEEE Transactions on Electron Devices, vol. 64, no. 8, pp. 3316–3323, Aug. 2017. https://doi.org/10.1109/TED.2017.2708691
A. Nipane, S. Jayanti, A. Borah, and J. T. Teherani, “Electrostatics of lateral p-n junctions in atomically thin materials,” Journal of Applied Physics, vol. 122, no. 19, p. 194501, Nov. 2017. https://doi.org/10.1063/1.4994047
A. Kerelsky, A. Nipane, D. Edelberg, D. Wang, X. Zhou, A. Motmaendadgar, H. Gao, S. Xie, K. Kang, J. Park, J. T. Teherani, and A. Pasupathy, “Absence of a Band Gap at the Interface of a Metal and Highly Doped Monolayer MoS2,” Nano Lett., Sep. 2017. https://doi.org/10.1021/acs.nanolett.7b01986
A. Kerelsky, A. Nipane, D. Edelberg, D. Wang, M. Cheng, A. Dadgar, H. Gao, K. Kang, J. Park, J. T. Teherani, and A. Pasupathy, “Band Structure Evolution in Vertically Contacted MoS2 Probed Using Scanning Tunneling Spectroscopy,” Bulletin of the American Physical Society, New Orleans, Louisiana, 2017, vol. Volume 62, Number 4. http://meetings.aps.org/Meeting/MAR17/Session/L32.12
J. T. Teherani, S. Agarwal, W. Chern, P. M. Solomon, E. Yablonovitch, and D. A. Antoniadis, “Auger generation as an intrinsic limit to tunneling field-effect transistor performance,” Journal of Applied Physics, vol. 120, no. 8, p. 084507, Aug. 2016. https://doi.org/10.1063/1.4960571
J. T. Teherani, “Fundamental limits of the switching abruptness of tunneling transistors,” Thesis, Massachusetts Institute of Technology, 2015. https://doi.org/1721.1/99853
J. T. Teherani, W. Chern, S. Agarwal, J. L. Hoyt, and D. A. Antoniadis, “A framework for generation and recombination in tunneling field-effect transistors,” Fourth Berkeley Symposium on Energy Efficient Electronic Systems (E3S), 2015, pp. 1–3. https://doi.org/10.1109/E3S.2015.7336797
T. Yu, J. T. Teherani, D. A. Antoniadis, and J. L. Hoyt, “Effects of substrate leakage and drain-side thermal barriers in In0.53Ga0.47As/GaAs0.5Sb0.5 quantum-well tunneling field-effect transistors,” Appl. Phys. Express, vol. 7, no. 9, p. 094201, Sep. 2014. https://doi.org/10.7567/APEX.7.094201
J. T. Teherani, W. Chern, D. A. Antoniadis, and J. L. Hoyt, “Ultra-Thin, High Quality HfO2 on Strained-Ge MOS Capacitors with Low Leakage Current,” ECS Trans., vol. 64, no. 6, pp. 267–271, Aug. 2014. https://doi.org/10.1149/06406.0267ecst
W. Chern, P. Hashemi, J. T. Teherani, D. A. Antoniadis, and J. L. Hoyt, “Record Hole Mobility at High Vertical Fields in Planar Strained Germanium on Insulator With Asymmetric Strain,” IEEE Electron Device Letters, vol. 35, no. 3, pp. 309–311, Mar. 2014. https://doi.org/10.1109/LED.2014.2300197
S. Agarwal, J. T. Teherani, J. L. Hoyt, D. A. Antoniadis, and E. Yablonovitch, “Engineering the Electron-Hole Bilayer Tunneling Field-Effect Transistor,” IEEE Transactions on Electron Devices, vol. 61, no. 5, pp. 1599–1606, May 2014. https://doi.org/10.1109/TED.2014.2312939
T. Yu, J. T. Teherani, D. A. Antoniadis, and J. L. Hoyt, “InGaAs/GaAsSb Quantum-Well Tunnel-FETs With Tunable Backward Diode Characteristics,” IEEE Electron Device Letters, vol. 34, no. 12, pp. 1503–1505, 2013. https://doi.org/10.1109/LED.2013.2287237
J. T. Teherani, T. Yu, D. A. Antoniadis, and J. L. Hoyt, “Electrostatic design of vertical tunneling field-effect transistors,” Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S), 2013, pp. 1–2. https://doi.org/10.1109/E3S.2013.6705872
J. T. Teherani and J. L. Hoyt, “A Physically-Intuitive Method for Calculation of the Local Lattice Constant from a High-Resolution Transmission Electron Microscopy Image by Fourier Analysis,” arXiv, Sep. 2013. http://arxiv.org/abs/1309.3155
J. T. Teherani, W. Chern, D. A. Antoniadis, and J. L. Hoyt, “Simulation of enhanced hole ballistic velocity in asymmetrically strained Germanium nanowire trigate p-MOSFETs,” IEEE International Electron Devices Meeting (IEDM), 2013, pp. 32.4.1-32.4.4. https://doi.org/10.1109/IEDM.2013.6724737
J. T. Teherani, S. Agarwal, E. Yablonovitch, J. L. Hoyt, and D. A. Antoniadis, “Impact of Quantization Energy and Gate Leakage in Bilayer Tunneling Transistors,” IEEE Electron Device Letters, vol. 34, no. 2, pp. 298–300, Feb. 2013. https://doi.org/10.1109/LED.2012.2229458
S. Agarwal, J. T. Teherani, J. L. Hoyt, D. A. Antoniadis, and E. Yablonovitch, “Optimization of the electron hole bilayer tunneling field effect transistor,” 71st Device Research Conference (DRC), 2013, pp. 109–110. https://doi.org/10.1109/DRC.2013.6633817
J. T. Teherani, W. Chern, D. A. Antoniadis, J. L. Hoyt, L. Ruiz, C. D. Poweleit, and J. Menéndez, “Extraction of large valence-band energy offsets and comparison to theoretical values for strained-Si/strained-Ge type-II heterostructures on relaxed SiGe substrates,” Phys. Rev. B, vol. 85, no. 20, p. 205308, May 2012. https://doi.org/10.1103/PhysRevB.85.205308
P. Hashemi, W. Chern, H. Lee, J. T. Teherani, Y. Zhu, J. Gonsalvez, G. G. Shahidi, and J. L. Hoyt, “Ultrathin Strained-Ge Channel P-MOSFETs With High-K/Metal Gate and Sub-1-nm Equivalent Oxide Thickness,” IEEE Electron Device Letters, vol. 33, no. 7, pp. 943–945, Jul. 2012. https://doi.org/10.1109/LED.2012.2195631
W. Chern, P. Hashemi, J. T. Teherani, T. Yu, Y. Dong, G. Xia, D. A. Antoniadis, and J. L. Hoyt, “High mobility high-K-all-around asymmetrically-strained Germanium nanowire trigate p-MOSFETs,” IEEE International Electron Devices Meeting (IEDM), 2012, pp. 16.5.1-16.5.4. https://doi.org/10.1109/IEDM.2012.6479055
P. M. Solomon, I. Lauer, A. Majumdar, J. T. Teherani, M. Luisier, J. Cai, and S. J. Koester, “Effect of Uniaxial Strain on the Drain Current of a Heterojunction Tunneling Field-Effect Transistor,” Electron Device Letters, IEEE, vol. 32, no. 4, pp. 464–466, 2011. https://doi.org/10.1109/LED.2011.2108993
J. T. Teherani, “Band-to-band tunneling in silicon diodes and tunnel transistors,” Thesis, MIT, Cambridge, MA, USA, 2010. https://doi.org/1721.1/60215
P. Hashemi, J. T. Teherani, and J. L. Hoyt, “Investigation of hole mobility in gate-all-around Si nanowire p-MOSFETs with high-K/metal-gate: Effects of hydrogen thermal annealing and nanowire shape,” IEEE International Electron Devices Meeting (IEDM), 2010, pp. 34.5.1-34.5.4. https://doi.org/10.1109/IEDM.2010.5703477
J. Beck, R. Scritchfield, B. Sullivan, J. T. Teherani, C.-F. Wan, M. Kinch, M. Ohlson, M. Skokan, L. Wood, P. Mitra, M. Goodwin, and J. Robinson, “Performance and modeling of the MWIR HgCdTe electron avalanche photodiode,” Proceedings of the SPIE, 2009, vol. 7298, pp. 729838-729838–17. https://doi.org/10.1117/12.819045
J. Beck, R. Scritchfield, B. Sullivan, J. T. Teherani, C.-F. Wan, M. Kinch, M. Ohlson, M. Skokan, L. Wood, P. Mitra, M. Goodwin, and J. Robinson, “Performance and Modeling of the MWIR HgCdTe Electron Avalanche Photodiode,” Journal of Elec Materi, vol. 38, no. 8, pp. 1579–1592, Aug. 2009. https://doi.org/10.1007/s11664-009-0684-8
H. F. Schaake, M. A. Kinch, D. Chandra, F. Aqariden, P. K. Liao, D. F. Weirauch, C.-F. Wan, R. E. Scritchfield, W. W. Sullivan, J. T. Teherani, and H. D. Shih, “High-Operating-Temperature MWIR Detector Diodes,” Journal of Elec Materi, vol. 37, no. 9, pp. 1401–1405, Sep. 2008. https://doi.org/10.1007/s11664-008-0423-6
A. Borah and J. T. Teherani, “Electrostatic Properties Simulation of Layered 2D Material Devices,” nanohub.org, 2017. https://doi.org/10.21981/D3C24QQ39
J. T. Teherani, “(Talk) Auger Generation as an Intrinsic Limit to Tunneling Field-Effect Transistor Performance,” nanohub.org, 2016. https://nanohub.org/resources/24982
J. T. Teherani, “Uniaxial and Biaxial Stress/Strain Calculator for Semiconductors,” nanohub.org, 2014. https://doi.org/10.4231/D33F4KN4J
